Hongyang Pan（潘鸿洋）

PhyLS: An AI-driven Physically Aware Synthesis Platform

Frontiers of Computer Science, 2026.

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EncyLogic: Logic Synthesis as Sequence Generation with Learned Priors and Physical Alignment

IEEE/ACM International Conference on Computer-Aided Design (ICCAD), San Jose, CA, USA, Nov. 8-12, 2026.

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PhySeqForm: A Data-Driven, Physical Synthesis Sequence Former

IEEE International Symposium on Circuits and Systems (ISCAS), Shanghai, China, May 24-27, 2026.

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PigMap3: A Physically Aware Incremental Mapping Framework with On-the-fly Post-Layout Critical Path Tracking

IEEE/ACM Asia and South Pacific Design Automation Conference (ASPDAC), Hong Kong, China, Jan. 19-22, 2026.

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PigMap2: A Physical Information Guided Technology Mapping Framework

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2025.

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Rethinking Logic Rewriting: Technology-Aware Subgraph Matching with Exact Synthesis

ACM Transactions on Design Automation of Electronic Systems (TODAES), 2025

ELMap: Area-Driven LUT Mapping with k-LUT Network Exact Synthesis

IEEE Design, Automation & Test in Europe Conference & Exhibition (DATE), Lyon, France, March 31 - April 2, 2025.

Physically Aware Synthesis Revisited: Guiding Technology Mapping with Primitive Logic Gate Placement

IEEE/ACM International Conference on Computer-Aided Design (ICCAD), New Jersey, NY, USA, Oct. 27–31, 2024.

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On Accelerating Domain-Specific MC-TS with Knowledge Retention and Efficient Parallelization for Logic Optimization

International Symposium of EDA (ISEDA), Xi'an, China, May 10–13, 2024.

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