PZTA: Accelerating Analog Circuit Sizing With A Transferable Circuit Theory-Inspired Pole-Zero Transient Assertion System
International Symposium of EDA (ISEDA), Hong Kong, China, May 9–12, 2025.
- † Corresponding authors
- Best Paper Award
Design Engineer, NVIDIA
M.Phil., Fudan University · 2023–2026
Design Engineer at NVIDIA. Graduate research at Fudan included optimization methods for circuit sizing.
With Prof. Fan Yang
International Symposium of EDA (ISEDA), Hong Kong, China, May 9–12, 2025.