Publications

You can also find my articles on my Google Scholar profile.

Books/Book Chpaters

B2b. Machine Learning for Analog Layout

B2a. Machine Learning for Analog Circuit Sizing

B1. CAD for Analog/Mixed-Signal Integrated Circuits

Journal Papers

J10. PARoute2: Enhanced Analog Routing via Performance-Drive Guidance Generation

J9. The Dawn of AI-Native EDA: Promises and Challenges of Large Circuit Models

J8. Domain Wall-Magnetic Tunnel Junction Analog Content Addressable Memory Using Current and Projected Data

J7. ISOP+: Machine Learning-Assisted Inverse Stack-Up Optimization for Advanced Package Design

J6. An In-Memory-Computing Charge-Domain Ternary CNN Classifier

J5. Hierarchical Analog and Mixed-Signal Circuit Placement Considering System Signal Flow

J4. 1- and 80-MS/s SAR ADCs in 40-nm CMOS With End-to-End Compilation

J3. Tutorial and Perspectives on MAGICAL: A Silicon-Proven Open-Source Analog IC Layout System

J2. Challenges and Opportunities Toward Fully Automated Analog Layout Design

J1. MAGICAL: An Open-Source Fully Automated Analog IC Layout System from Netlist to GDSII

Conference Papers

C48. MARIO: A Superadditive Multi-Algorithm Interworking Optimization Framework for Analog Circuit Sizing

C47. Decoupling Analog Circuit Representation from Process for Behavior-Centric Optimization

C46. GPU Acceleration of A High-precision Stochastic Solver for Steady-state Thermal Analysis with Robin Boundary Conditions

C45. Adaptive Preconditioning Guided by Divergence Analysis for Enhanced VLSI Global Placement

C44. Multi-Armed Bandits-Based Exploring and Exploiting the High-Dimensional Design Space for Analog Circuit with Adjoint Sensitivity

C43. Multi-Armed Bandits-Based Exploring and Exploiting the High-Dimensional Design Space for Analog Circuit with Adjoint Sensitivity

C42. Hybrid Automation in Analog Sizing: Synergizing Designer Intuition with Multi-Objective Optimization for Gain-Boosted Amplifiers

C41. DAMIL-DCIM: A Digital CIM Layout Synthesis Framework with Dataflow-Aware Floorplan and MILP-Based Detailed Placement

C40. ELMap: Area-Driven LUT Mapping with k-LUT Network Exact Synthesis

C39. LiDAR: Automated Curvy Waveguide Detailed Routing for Large-Scale Photonic Integrated Circuits

C38. HeLO: A Heterogeneous Logic Optimization Framework by Hierarchical Clustering and Graph Learning

C37. AnalogGym: An Open and Practical Testing Suite for Analog Circuit Synthesis

C36. Physically Aware Synthesis Revisited: Guiding Technology Mapping with Primitive Logic Gate Placement

C35. Revisiting Sensitivity-based Analog Sizing with Derivative-aware Bayesian Optimization and Error-Suppressed Adjoint Analysis

C34. AI-Enabled Layout Automation for Analog and RF IC: Current Status and Future Directions

C33. Performance-driven Analog Routing via Heterogeneous 3DGNN and Potential Relaxation

C32. On Accelerating Domain-Specific MC-TS with Knowledge Retention and Efficient Parallelization for Logic Optimization

C31. Universal Process Migration Solution of MAGICAL for Analog IC Layout Automation

C30. A Data-Driven Analog Circuit Synthesizer with Automatic Topology Selection and Sizing

C29. Multi-Electrostatics Based Placement for Non-Integer Multiple-Height Cells

C28. Performance-Driven Analog Layout Automation: Current Status and Future Directions

C27. A Study on Exploring and Exploiting the High-dimensional Design Space for Analog Circuit Design Automation

C26. ISOP-Yield: Yield-Aware Stack-Up Optimization for Advanced Package using Machine Learning

C25. AlphaSyn: Logic Synthesis Optimization with Efficient Monte Carlo Tree Search

C24. Practical Layout-Aware Analog/Mixed-Signal Design Automation with Bayesian Neural Networks

C23. ISOP: Machine Learning-Assisted Inverse Stack-Up Optimization for Advanced Package Design

C22. Joint Optimization of Sizing and Layout for AMS Designs: Challenges and Opportunities

C21. Reinforcement Learning Guided Detailed Routing for FinFET Custom Circuits

C20. TAG: Learning Circuit Spatial Embedding From Layouts

C19. Fuse and Mix: MACAM-Enabled Analog Activation for Energy-Efficient Neural Acceleration

C18. AutoCRAFT: Layout Automation for Custom Circuits in Advanced FinFET Technologies

C17. Automating Analog Constraint Extraction: From Heuristics to Learning

C16. Reinforcement Learning for Electronic Design Automation: Case Studies and Perspectives

C15. Generative-Adversarial-Network-Guided Well-Aware Placement for Analog Circuits

C14. OpenSAR: An OpenSource Automated End-to-end SARADC Compiler

C13. Universal Symmetry Constraint Extraction for Analog and Mixed-Signal Circuits with Graph Neural Networks

C12. Optimizer Fusion: Efficient Training with Better Locality and Parallelism

C11. An In-Memory-Computing Charge-Domain Ternary CNN Classifier

C10. MAGICAL 1.0: An Open-Source Fully-Automated AMS Layout Synthesis Framework Verified With a 40-nm 1GS/s Δ∑ ADC

C9. Exploring Logic Optimizations with Reinforcement Learning and Graph Convolutional Network

C8. Toward Silicon-Proven Detailed Routing for Analog and Mixed-Signal Circuits

C7. Effective Analog/Mixed-Signal Circuit Placement Considering System Signal Flow

C6. An Efficient Training Framework for Reversible Neural Architectures

C5. Closing the Design Loop: Bayesian Optimization Assisted Hierarchical Analog Layout Synthesis

C4. Towards Decrypting the Art of Analog Layout: Placement Quality Prediction via Transfer Learning

C3. S3DET: Detecting System Symmetry Constraints for Analog Circuits with Graph Similarity

C2. MAGICAL: Toward Fully Automated Analog IC Layout Leveraging Human and Machine Intelligence

C1. GeniusRoute: A New Routing Paradigm Using Generative Neural Network Guidance for Analog Circuits