Publications

Google Scholar ↗

2027

C67. From Communities to Coordinates: Hierarchical Clustering-Guided Placement for Large-Scale FPGAs

Ke Li, Pengju Zhang, Zhiyu Zheng, Yuhao Ren, Keren Zhu, Zhiang Wang† and Xuan Zeng†

IEEE/ACM Asia and South Pacific Design Automation Conference (ASPDAC), Tokyo, Japan, Jan. 25-28, 2027.

† Corresponding authors
Accepted

2026

J21. ULTRA-2.5D: An Analytical Placement Framework for Ultra-Large-Scale Multi-Reticle Chiplet Systems

Jinhong Huang, Yuyan Wang, Boxiang Song, Chengkai Zhu, Yuman Zeng, Jiayao Li, Keren Zhu†, Lang Feng, Changhao Yan†, Chixiao Chen, and Xuan Zeng†

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2026.

† Corresponding authors

J20. Beyond Surrogate Accuracy: Credibility-Aware LLM-Guided Design Space Exploration for High-Level Synthesis

Yujie Yan, Guanhua Chen, Yukang Chen, Jiaxin Huang, Jianyi Cheng, and Keren Zhu†

ACM Transactions on Reconfigurable Technology and Systems (TRETS), 2026.

FPT 2026 Journal Track
† Corresponding author

J19. AnalogGym-Opt: An Open and Practical Optimization Infrastructure for LLM-Assisted Analog Circuit Sizing with GRPO

Jintao Li, Haochang Zhi, Yongji Long, Weixuan Liu, Yanhan Zeng, Keren Zhu, Shui Yu†, and Yun Li†

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2026.

† Corresponding authors

J18. A Behavior-Centric Methodology for High-Performance Amplifier Sizing

Haochang Zhi*, Jintao Li*, Keren Zhu, Yun Li, Weiwei Shan†, and Wanyuan Qu†

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2026.

† Corresponding authors
* Equal contributions

J17. S3HDBO: Sensitivity-Guided Search Region Scaling High-Dimensional Bayesian Optimization for BSIM-CMG Parameter Extraction

Ruiyu Lyu, Zhaori Bi†, Keren Zhu, Ye Lu and Xuan Zeng†

IEEE Transactions on Electron Devices, 2026.

† Corresponding authors

J16. PhyLS: An AI-driven Physically Aware Synthesis Platform

Hongyang Pan, Cunqing Lan, Zhiang Wang†, Keren Zhu†

Frontiers of Computer Science, 2026.

† Corresponding authors

J15. An Accurate and Efficient Stochastic Solver for Transient Thermal Analysis with Mixed Boundary Conditions

Zhixuan Dong, Yuan Meng, Changhao Yan, Zhaori Bi, Keren Zhu, Sheng-Guo Wang, Dian Zhou, and Xuan Zeng

IEEE Transactions on Components, Packaging and Manufacturing Technology, 2026.

C68. Beyond Capacity Checks: Read-Trace Consistency in Systolic-Array Simulator Evaluation

Yixuan Zhuang†, Shiting Wang, Ruiyao Qin, and Keren Zhu†

International Conference on Integrated Circuits and Microsystems (ICICM), Xi'an, China, October 16–18, 2026.

† Corresponding authors
Accepted
(Best Presentation)

C66. EncyLogic: Logic Synthesis as Sequence Generation with Learned Priors and Physical Alignment

Zijian Jiang*, Chenyu Li*, Cunqing Lan, Hongyang Pan, Jintao Li, Zhiang Wang and Keren Zhu†

IEEE/ACM International Conference on Computer-Aided Design (ICCAD), San Jose, CA, USA, Nov. 8-12, 2026.

† Corresponding authors
* Equal contributions
Accepted

C65. GTStress: A Graph-Augmented Neural Framework for Thermal Stress Simulation of Parameterized TSV Arrays with Superposed Physical Priors and Query-Graph Fusion

Zhixuan Dong, Chenlong He, Changhao Yan†, Zhaori Bi, Keren Zhu, Bowen Jia and Xuan Zeng†

IEEE/ACM International Conference on Computer-Aided Design (ICCAD), San Jose, CA, USA, Nov. 8-12, 2026.

† Corresponding authors
Accepted

C64. Analytical Chiplet Placement with Force-Directed Guidance and Chiplet Bridging for Multi-Reticle Interposers

Jiayao Li, Lang Feng†, Jinhong Huang, Keren Zhu and Zhongfeng Wang†

IEEE/ACM International Conference on Computer-Aided Design (ICCAD), San Jose, CA, USA, Nov. 8-12, 2026.

† Corresponding authors
Accepted

C63. CNE-PDN: Joint Optimization of PDN Geometry and TSV Layout via Component-Level Neural Parasitic Extraction for 2.5D IC

Chengkai Zhu, Jinhong Huang, Boxiang Song, Xihan Yang, Siwen Wang, Yiyang Zhao, Keren Zhu† and Changhao Yan†

IEEE/ACM International Conference on Computer-Aided Design (ICCAD), San Jose, CA, USA, Nov. 8-12, 2026.

† Corresponding authors
Accepted

C62. An Efficient Framework for Soft Error Analysis and Selective Hardening via Graph Selective State-Space Model

Borui Li, Yuyan Wang, Changhao Yan†, Keren Zhu, Zhaori Bi, Nan Zhang, Zhipeng Liu and Xuan Zeng†

IEEE/ACM International Conference on Computer-Aided Design (ICCAD), San Jose, CA, USA, Nov. 8-12, 2026.

† Corresponding authors
Accepted

C61. PeRIFi: Physics-Infused RF Inverse Design with Parametric Data-Efficient Feasible-Region Sampling

Siwen Wang, Keren Zhu†, Hyunsu Chae, Zhaori Bi, Zhiang Wang, Changhao Yan and Xuan Zeng†

IEEE/ACM Design Automation Conference (DAC), Long Beach, CA, July 26-29, 2026.

† Corresponding authors
Accepted

C60. A Physically-aware Framework for Joint MBFF Synthesis with OPTICS-based Debanking

Benchao Zhu, Jiawei Li, Yang Liu, Jianli Chen†, Keren Zhu†

ACM Great Lakes Symposium on VLSI (GLSVLSI), Finger Lakes, NY, USA, June 22-24, 2026.

† Corresponding authors
Accepted

C59. PhySeqForm: A Data-Driven, Physical Synthesis Sequence Former

Cunqing Lan*, Zijian Jiang*, Hongyang Pan†, Zhiang Wang and Keren Zhu†

IEEE International Symposium on Circuits and Systems (ISCAS), Shanghai, China, May 24-27, 2026.

† Corresponding authors
* Equal contributions
Accepted

C58. HOLMES: Hierarchical Optimization with poLygonal ModEling for Large-Scale AMS Placement

Guanhua Chen, Yujie Yan, Jiahua Liu, Zecheng Xu, Linxi Qiu, Yumao Wu, Zhiang Wang, Changhao Yan, Zhaori Bi, Keren Zhu†

IEEE International Symposium on Circuits and Systems (ISCAS), Shanghai, China, May 24-27, 2026.

† Corresponding authors
Accepted

C57. Layout-Aware Standard Cell Synthesis via Reparameterization Multi-Task Bayesian Optimization

Zhouyang Wu*, Ruiyu Lyu*, Keren Zhu†, Zhiang Wang, Zhaori Bi, Changhao Yan, Xuan Zeng†

IEEE International Symposium on Circuits and Systems (ISCAS), Shanghai, China, May 24-27, 2026.

† Corresponding authors
* Equal contributions
Accepted

C56. RC-Scaled Timing-Driven Routing: Bridging Targeted Timing Optimization and Massively Parallel Global Routing

Chuyu Wang, Zecheng Xu, Boxiang Song, Zhiang Wang†, Fan Yang†, Keren Zhu† and Xuan Zeng†

IEEE International Symposium on Circuits and Systems (ISCAS), Shanghai, China, May 24-27, 2026.

† Corresponding authors
Accepted

C55. LENS-HLS: LLM-Enhanced Learning-based Design Space Exploration for High-Level Synthesis

Yujie Yan, Guanhua Chen, Keren Zhu†

IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM), Atlanta, GA, USA, May 13-16, 2026.

† Corresponding authors
Accepted (Extended Abstract)

C54. Submodular Maximization-inspired Adaptive Routing Bend Space Planning

Siting Liu, Peng Xu, Peiyu Liao, Keren Zhu, Yibo Lin, and Bei Yu

IEEE Design, Automation & Test in Europe Conference & Exhibition (DATE), Verona, Italy, Apr. 20-22, 2026.

Accepted

C53. PigMap3: A Physically Aware Incremental Mapping Framework with On-the-fly Post-Layout Critical Path Tracking

Hongyang Pan*, Cunqing Lan*, Zhiang Wang, Xuan Zeng, Fan Yang, Keren Zhu†

IEEE/ACM Asia and South Pacific Design Automation Conference (ASPDAC), Hong Kong, China, Jan. 19-22, 2026.

† Corresponding authors
* Equal contributions

2025

J14. PigMap2: A Physical Information Guided Technology Mapping Framework

Cunqing Lan*, Hongyang Pan*, Zhiang Wang†, Xuan Zeng, Fan Yang and Keren Zhu†,

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2025.

† Corresponding authors
* Equal contributions

J13. DAMIL-DCIM+: Automated Dataflow-Aware Layout Synthesis for Digital CIM with Self-Assembled Bitcell Units and MILP-Based Optimization

Chuyu Wang*, Xinglong Yan*, Zecheng Xu∗, Ke Hu, Keren Zhu†, Shuo Li, Fan Yang and Xuan Zeng†

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2025.

† Corresponding authors
* Equal contributions

J12. An Iterative FEM Solver for IC Electromagnetic Analysis via Hybrid Geometric-Algebraic Partitioning and Neural Network Optimization

Mingtao Li, Changhao Yan, Tao Cui, Liguo Jiang, Wenliang Dai, Zhaori Bi, Keren Zhu, and Xuan Zeng

IEEE Transactions on Microwave Theory and Techniques (TMTT), 2025

J11. Rethinking Logic Rewriting: Technology-Aware Subgraph Matching with Exact Synthesis

Hongyang Pan, Keren Zhu, Fan Yang, Xuan Zeng, Sen Liu, Yong Xiao, Yun Shao, and Zhufei Chu

ACM Transactions on Design Automation of Electronic Systems (TODAES), 2025

J10. PARoute2: Enhanced Analog Routing via Performance-Drive Guidance Generation

Peng Xu, Jindong Tu, Guojin Chen, Keren Zhu, Tinghuan Chen, Tsung-Yi Ho, and Bei Yu

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2025.

C52. HOLMES-HLS: Holistic Optimization and Learning-based Multi-model Exploration System for High-Level Synthesis

Yujie Yan*, Guanhua Chen*, Ruiyu Lyu, Huizhen Kuang, Kaiwen Zhou, Hao Chen, Lingli Wang, Keren Zhu†

International Conference on Field Programmable Technology (FPT) , Shanghai, China, Dec. 2-5, 2025.

† Corresponding authors
* Equal contributions

C51. LCTMwalk: GPU-Accelerated Transient Thermal Simulation for Liquid-Cooled 2.5D/3D ICs via Random Walks on Circuit Networks of Modified Compact Thermal Models

Zhixuan Dong, Yonghan Luo, Yuan Meng, Changhao Yan, Zhaori Bi, Keren Zhu, Sheng-Guo Wang, Dian Zhou and Xuan Zeng

IEEE/ACM International Conference on Computer-Aided Design (ICCAD), Munich, Germany, Oct. 26-30, 2025.

C50. Seeing Through Designs: Attention-Based Knowledge Transfer for Preference-Guided Microarchitecture Search

Yiyang Zhao, Xuyang Zhao, Zhaori Bi, Ming Zhu, Qiwei Zhan, Keren Zhu, Fan Yang, Changhao Yan, Dian Zhou and Xuan Zeng

IEEE/ACM International Conference on Computer-Aided Design (ICCAD), Munich, Germany, Oct. 26-30, 2025.

C49. NSTherm: An Error-Bounded Network-Stochastic Fusion Thermal Simulator for Geometry-Adaptable Chiplets via Diffeomorphic Mapping and Neural- Guided Variance Reduction

Yuan Meng, Yuyan Wang, Zhixuan Dong, Yonghan Luo, Changhao Yan, Keren Zhu, Zhaori Bi, Shengguo Wang, Dian Zhou and Xuan Zeng

IEEE/ACM International Conference on Computer-Aided Design (ICCAD), Munich, Germany, Oct. 26-30, 2025.

C48. MARIO: A Superadditive Multi-Algorithm Interworking Optimization Framework for Analog Circuit Sizing

Wangzhen Li, Yuan Meng, Ruiyu Lyu, Changhao Yan, Keren Zhu, Zhaori Bi, Dian Zhou and Xuan Zeng

IEEE/ACM Design Automation Conference (DAC) , San Francisco, USA, Jun. 22–25, 2025.

C47. Decoupling Analog Circuit Representation from Process for Behavior-Centric Optimization

Jintao Li, Haochang Zhi, Jiang Xiao, Keren Zhu^* and Yun Li^*,

IEEE/ACM Design Automation Conference (DAC) , San Francisco, USA, Jun. 22–25, 2025.

* corresponding authors

C46. GPU Acceleration of A High-precision Stochastic Solver for Steady-state Thermal Analysis with Robin Boundary Conditions

Yonghan Luo, Yuyan Wang, Zhixuan Dong, Changhao Yan, Zhaori Bi, Keren Zhu, Shengguo Wang, and Xuan Zeng

International Symposium of EDA (ISEDA), Hong Kong, China, May 9–12, 2025.

C45. Adaptive Preconditioning Guided by Divergence Analysis for Enhanced VLSI Global Placement

Liwen Jiang, Ruiyu Lyu, Fan Yang, and Keren Zhu†

International Symposium of EDA (ISEDA), Hong Kong, China, May 9–12, 2025.

† Corresponding authors

C44. PZTA: Accelerating Analog Circuit Sizing With A Transferable Circuit Theory-Inspired Pole-Zero Transient Assertion System

Xiaoyu Zhong, Jintao Li, Zhaori Bi, Yun Li, Fan Yang, Xuan Zeng, and Keren Zhu†

International Symposium of EDA (ISEDA), Hong Kong, China, May 9–12, 2025.

† Corresponding authors
Best Paper Award

C43. Multi-Armed Bandits-Based Exploring and Exploiting the High-Dimensional Design Space for Analog Circuit with Adjoint Sensitivity

Ruiyu Lyu, Yuan Meng, Zhaori Bi, Keren Zhu, Changhao Yan, Fan Yang, and Xuan Zeng

International Symposium of EDA (ISEDA), Hong Kong, China, May 9–12, 2025.

C42. Hybrid Automation in Analog Sizing: Synergizing Designer Intuition with Multi-Objective Optimization for Gain-Boosted Amplifiers

Yue Huang, Wangzhen Li, Xiaochuan Peng, Keren Zhu, Fan Yang, and Xuan Zeng

International Symposium of EDA (ISEDA), Hong Kong, China, May 9–12, 2025.

C41. DAMIL-DCIM: A Digital CIM Layout Synthesis Framework with Dataflow-Aware Floorplan and MILP-Based Detailed Placement

Chuyu Wang, Ke Hu, Fan Yang, Keren Zhu^*, and Xuan Zeng^*

IEEE Design, Automation & Test in Europe Conference & Exhibition (DATE), Lyon, France, March 31 - April 2, 2025.

* corresponding authors

C40. ELMap: Area-Driven LUT Mapping with k-LUT Network Exact Synthesis

Hongyang Pan, Keren Zhu, Fan Yang, Zhufei Chu and Xuan Zeng

IEEE Design, Automation & Test in Europe Conference & Exhibition (DATE), Lyon, France, March 31 - April 2, 2025.

C39. LiDAR: Automated Curvy Waveguide Detailed Routing for Large-Scale Photonic Integrated Circuits

Hongjian Zhou, Keren Zhu, and Jiaqi Gu

ACM International Symposium on Physical Design (ISPD), Austin, Mar. 16–19, 2025.

preprint

C38. HeLO: A Heterogeneous Logic Optimization Framework by Hierarchical Clustering and Graph Learning

Yuan Pu, Fangzhou Liu, Zhuolun He, Keren Zhu, Rongliang Fu, Ziyi Wang, Tsung-Yi Ho, and Bei Yu

ACM International Symposium on Physical Design (ISPD), Austin, Mar. 16–19, 2025.

Best Paper Award Nomination

2024

J9. The Dawn of AI-Native EDA: Promises and Challenges of Large Circuit Models

Tsung-Yi Ho, Sadaf Khan, Jinwei Liu, Yi Liu, Zhengyuan Shi, Ziyi Wang, Qiang Xu, Evangeline F.Y. Young, Bei Yu, Ziyang Zheng, Binwu Zhu, Keren Zhu, Yiqi Che, Yun Liang, Yibo Lin, Guojie Luo, Guangyu Sun, Runsheng Wang, Xinming Wei, Chenhao Xue, Haoyi Zhang, Zuodong Zhang, Yuxiang Zhao, Sunan Zou, Lei Chen, Yu Huang, Min Li, Dimitrios Tsaras, Mingxuan Yuan, Hui-Ling Zhen, Zhufei Chu, Wenji Fang, Xingquan Li and Zhiyao Xie

SCIENCE CHINA Information Sciences, 2024.

Arxiv

J8. Domain Wall-Magnetic Tunnel Junction Analog Content Addressable Memory Using Current and Projected Data

Harrison Jin, Hanqing Zhu, Keren Zhu, Thomas Leonard, Jaesuk Kwon, Mahshid Alamdar, Kwangseok Kim, Jungsik Park, Naoki Hase, David Z. Pan, Jean Anne C. Incorvia

IEEE Transactions on Nanotechnology, 2024.

Arxiv

C37. AnalogGym: An Open and Practical Testing Suite for Analog Circuit Synthesis

Jintao Li, Haochang Zhi, Ruiyu Lyu, Wangzhen Li, Zhaori Bi^*, Keren Zhu^*, Yanhan Zeng, Weiwei Shan, Changhao Yan, Fan Yang, Yun Li^*, and Xuan Zeng^*

IEEE/ACM International Conference on Computer-Aided Design (ICCAD), New Jersey, NY, USA, Oct. 27–31, 2024.

Github Repo | preprint
* corresponding authors
(Invited)

C36. Physically Aware Synthesis Revisited: Guiding Technology Mapping with Primitive Logic Gate Placement

Hongyang Pan, Cunqing Lan, Yiting Liu, Zhiang Wang, Li Shang, Xuan Zeng, Fan Yang and Keren Zhu†

IEEE/ACM International Conference on Computer-Aided Design (ICCAD), New Jersey, NY, USA, Oct. 27–31, 2024.

preprint
(Accepted)
† Corresponding author

C35. Revisiting Sensitivity-based Analog Sizing with Derivative-aware Bayesian Optimization and Error-Suppressed Adjoint Analysis

Ruiyu Lyu, Aidong Zhao, Yuan Meng, Zhaori Bi, Keren Zhu, Changhao Yan, Fan Yang, Dian Zhou and Xuan Zeng

IEEE/ACM International Conference on Computer-Aided Design (ICCAD), New Jersey, NY, USA, Oct. 27–31, 2024.

(Accepted)

C34. AI-Enabled Layout Automation for Analog and RF IC: Current Status and Future Directions

Chuyu Wang, Fan Yang, and Keren Zhu†

IEEE International Symposium on Radio-Frequency Integration Technology (RFIT), Chengdu, China, Aug. 28–30, 2024.

† Corresponding authors

C33. Performance-driven Analog Routing via Heterogeneous 3DGNN and Potential Relaxation

Peng Xu, Guojin Chen, Keren Zhu, Tinghuan Chen, Tsung-Yi Ho, and Bei Yu

IEEE/ACM Design Automation Conference (DAC) , San Francisco, USA, Jun. 23–27, 2024.

C32. On Accelerating Domain-Specific MC-TS with Knowledge Retention and Efficient Parallelization for Logic Optimization

Cunqing Lan, Xinyao Wang, Zijian Jiang, Hongyang Pan, Keren Zhu†, Zhaori Bi, Changhao Yan and Xuan Zeng

International Symposium of EDA (ISEDA), Xi'an, China, May 10–13, 2024.

† Corresponding author

C31. Universal Process Migration Solution of MAGICAL for Analog IC Layout Automation

Yufeng Wei, Yifan Xu, Keren Zhu and Ye Lu

2024 Conference of Science and Technology for Integrated Circuits (CSTIC)

C30. A Data-Driven Analog Circuit Synthesizer with Automatic Topology Selection and Sizing

Souradip Poddar, Ahmet Budak, Linran Zhao, Chen-Hao Hsu, Supriyo Maji, Keren Zhu, Yaoyao Jia, and David Z. Pan,

IEEE Design, Automation & Test in Europe Conference & Exhibition (DATE), Valencia, Spain, March 25 - 27, 2024.

C29. Multi-Electrostatics Based Placement for Non-Integer Multiple-Height Cells

Yu Zhang, Yuan Pu, Fangzhou Liu, Peiyu Liao, Kaiyuan Chao, Keren Zhu, Yibo Lin, and Bei Yu,

ACM International Symposium on Physical Design (ISPD) , Taipei, March 12 - 15, 2024.

C28. Performance-Driven Analog Layout Automation: Current Status and Future Directions

Peng Xu, Jintao Li, Tsung-Yi Ho, Bei Yu, and Keren Zhu†,

IEEE/ACM Asia and South Pacific Design Automation Conference (ASPDAC), Incheon, S. Korea, Jan 22-25, 2024.

† Corresponding authors
Invited

C27. A Study on Exploring and Exploiting the High-dimensional Design Space for Analog Circuit Design Automation

Ruiyu Lyu, Yuan Meng, Zhaori Bi, Keren Zhu, Fan Yang, Changhao Yan, Dian Zhou, and Xuan Zeng,

IEEE/ACM Asia and South Pacific Design Automation Conference (ASPDAC), Incheon, S. Korea, Jan 22-25, 2024.

Invited

C26. ISOP-Yield: Yield-Aware Stack-Up Optimization for Advanced Package using Machine Learning

Hyunsu Chae, Keren Zhu, Bhyrav Mutnury, Zixuan Jiang, Daniel de Araujo, Adam Klivans, and David Z. Pan,

IEEE/ACM Asia and South Pacific Design Automation Conference (ASPDAC), Incheon, S. Korea, Jan 22-25, 2024.

Accepted

2023

J7. ISOP+: Machine Learning-Assisted Inverse Stack-Up Optimization for Advanced Package Design

Hyunsu Chae, Keren Zhu, Bhyrav Mutnury, Doug Wallace, Doug Winterburg, Daniel DeAraujo, Jay Reddy, Adam Klivans and David Z. Pan

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2023.

J6. An In-Memory-Computing Charge-Domain Ternary CNN Classifier

Xiangxing Yang, Keren Zhu, Xiyuan Tang, Meizhi Wang, Mingtao Zhan, Nanshu Lu, Jaydeep P. Kulkarni, David Z. Pan, Yongpan Liu and Nan Sun

IEEE Journal of Solid State Circuits (JSSC), 2023.

J5. Hierarchical Analog and Mixed-Signal Circuit Placement Considering System Signal Flow

Keren Zhu, Hao Chen, Mingjie Liu, and David Z. Pan

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2023.

J4. 1- and 80-MS/s SAR ADCs in 40-nm CMOS With End-to-End Compilation

Mingjie Liu*, Xiyuan Tang*, Keren Zhu, Hao Chen, Nan Sun, and David Z. Pan

IEEE Solid-State Circuits Letters, 2023.

* indicates equal contributions in alphabetic order)

C25. AlphaSyn: Logic Synthesis Optimization with Efficient Monte Carlo Tree Search

Zehua Pei, Fangzhou Liu, Zhuolun He, Guojin Chen, Haisheng Zheng, Keren Zhu and Bei Yu,

IEEE/ACM International Conference on Computer-Aided Design (ICCAD), San Francisco, CA, October 29 - November 2, 2023.

Accepted

C24. Practical Layout-Aware Analog/Mixed-Signal Design Automation with Bayesian Neural Networks

Ahmet F. Budak, Keren Zhu and David Z. Pan

IEEE/ACM International Conference on Computer-Aided Design (ICCAD), San Francisco, CA, October 29 - November 2, 2023.

C23. ISOP: Machine Learning-Assisted Inverse Stack-Up Optimization for Advanced Package Design

Hyunsu Chae, Bhyrav Mutnury, Keren Zhu, Doug Wallace, Doug Winterburg, Daniel DeAraujo, Jay Reddy, Adam Klivans and David Z. Pan

IEEE Design, Automation & Test in Europe Conference & Exhibition (DATE), Antwerp, Belgium, April 17- 19, 2023.

C22. Joint Optimization of Sizing and Layout for AMS Designs: Challenges and Opportunities

Ahmet F Budak, Keren Zhu, Hao Chen, Souradip Poddar, Linran Zhao, Yaoyao Jia and David Z Pan

ACM International Symposium on Physical Design (ISPD), Virtual Conference, March 26-29, 2023.

Invited

C21. Reinforcement Learning Guided Detailed Routing for FinFET Custom Circuits

Hao Chen, Kai-Chieh Hsu, Walker J. Turner, Po-Hsuan Wei, Keren Zhu, David Z. Pan and Haoxing Ren

ACM International Symposium on Physical Design (ISPD), Virtual Conference, March 26-29, 2023.

2022

B2b. Machine Learning for Analog Layout

Steven M. Burns, Hao Chen, Tonmoy Dhar, Ramesh Harjani, Jiang Hu, Nibedita Karmokar, Kishor Kunal, Yaguang Li, Yishuang Lin, Mingjie Liu, Meghna Madhusudan, Parijat Mukherjee, David Z. Pan, Jitesh Poojary, S. Ramprasath, Sachin S. Sapatnekar, Arvind K. Sharma, Wenbin Xu, Soner Yaldiz, and Keren Zhu,

Machine Learning Applications in Electronic Design Automation, Springer, 2022

Authors in alphabetic order

B2a. Machine Learning for Analog Circuit Sizing

Ahmet F. Budak*, Shuhan Zhang*, Mingjie Liu, Wei Shi, Keren Zhu, and David Z. Pan,

Machine Learning Applications in Electronic Design Automation, Springer, 2022

* Equal contribution

B1. CAD for Analog/Mixed-Signal Integrated Circuits

Mohamed B. Alawieh, Ahmet F. Budak, Hao Chen, Mingjie Liu, David Z. Pan, Wei Shi, Xiyuan Tang, Shuhan Zhang and Keren Zhu

Advances in Semiconductor Technologies: Selected Topics Beyond Conventional CMOS, Wiley-IEEE Press., 2022

Authors in alphabetic order

J3. Tutorial and Perspectives on MAGICAL: A Silicon-Proven Open-Source Analog IC Layout System

Keren Zhu, Hao Chen, Mingjie Liu and David Z. Pan

IEEE Transactions on Circuits and Systems–II: Express Briefs (TCAS-II), 2022.

Invited

C20. TAG: Learning Circuit Spatial Embedding From Layouts

Keren Zhu, Hao Chen, Walker Turner, George Kokai, Po-Hsuan Wei, David Z. Pan, and Haoxing Ren

IEEE/ACM International Conference on Computer-Aided Design (ICCAD), San Diego, Oct. 30–Nov. 3, 2022.

Best Paper Candidate Nominated from Track

C19. Fuse and Mix: MACAM-Enabled Analog Activation for Energy-Efficient Neural Acceleration

Hanqing Zhu, Keren Zhu, Jiaqi Gu, Harrison Jin, Ray Chen, Jean Anne Incorvia, and David Z. Pan

IEEE/ACM International Conference on Computer-Aided Design (ICCAD), San Diego, Oct. 30–Nov. 3, 2022.

C18. AutoCRAFT: Layout Automation for Custom Circuits in Advanced FinFET Technologies

Hao Chen, Walker J. Turner, Sanquan Song, Keren Zhu, George F. Kokai, Brian Zimmer, C. Thomas Gray, Brucek Khailany, David Z. Pan, and Haoxing Ren

ACM International Symposium on Physical Design (ISPD), Virtual Conference, March 27-30, 2022.

Invited

C17. Automating Analog Constraint Extraction: From Heuristics to Learning

Keren Zhu, Hao Chen, Mingjie Liu, and David Z. Pan

IEEE/ACM Asia and SouthPacific Design Automation Conference (ASPDAC), Virtual Conference, January 17-20, 2022.

Invited

C16. Reinforcement Learning for Electronic Design Automation: Case Studies and Perspectives

Ahmet F. Budak*, Zixuan Jiang*, Keren Zhu, Azalia Mirhoseini, Anna Goldie, and David Z. Pan

IEEE/ACM Asia and SouthPacific Design Automation Conference (ASPDAC), Virtual Conference, January 17-20, 2022.

Invited
*indicates equal contributions

C15. Generative-Adversarial-Network-Guided Well-Aware Placement for Analog Circuits

Keren Zhu, Hao Chen, Mingjie Liu, Xiyuan Tang, Wei Shi, Nan Sun, and David Z. Pan

IEEE/ACM Asia and SouthPacific Design Automation Conference (ASPDAC), Virtual Conference, January 17-20, 2022.

2021

C14. OpenSAR: An OpenSource Automated End-to-end SARADC Compiler

Mingjie Liu, Xiyuan Tang, Keren Zhu, Hao Chen, Nan Sun, and David Z. Pan

IEEE/ACM International Conference on Computer-Aided Design (ICCAD), Virtual Conference, November 1-5, 2021.

source codes

C13. Universal Symmetry Constraint Extraction for Analog and Mixed-Signal Circuits with Graph Neural Networks

Hao Chen, Keren Zhu, Mingjie Liu, Xiyuan Tang, Nan Sun, and David Z. Pan

ACM/IEEE Design Automation Conference (DAC), San Francisco, CA, December 5-9, 2021.

C12. Optimizer Fusion: Efficient Training with Better Locality and Parallelism

Zixuan Jiang, Jiaqi Gu, Mingjie Liu, Keren Zhu and David Z. Pan

International Conference on Learning Representations (ICLR)Workshop, Hardware Aware Efficient Training (HAET), May 07, 2021.

C11. An In-Memory-Computing Charge-Domain Ternary CNN Classifier

Xiangxing Yang, Keren Zhu, Xiyuan Tang, Meizhi Wang, Mingtao Zhan, Nanshu Lu, Jaydeep P. Kulkarni, David Z. Pan, Yongpan Liu and Nan Sun

2021 IEEE Custom Integrated Circuits Conference (CICC), Virtual Event, April 25-30, 2021.

slides
Best Student Paper Award Nomination

C10. MAGICAL 1.0: An Open-Source Fully-Automated AMS Layout Synthesis Framework Verified With a 40-nm 1GS/s Δ∑ ADC

Hao Chen*, Mingjie Liu*, Xiyuan Tang*, Keren Zhu*, Abhishek Mukherjee, Nan Sun and David Z. Pan

2021 IEEE Custom Integrated Circuits Conference (CICC), Virtual Event, April 25-30, 2021.

slides | video
*indicates equal contributions

2020

J2. Challenges and Opportunities Toward Fully Automated Analog Layout Design

Hao Chen*, Mingjie Liu *, Xiyuan Tang*, Keren Zhu *, Nan Sun and David Z. Pan

Journal of Semiconductors, 2020.

Invited
Featured on the cover
* In alphabetic order

J1. MAGICAL: An Open-Source Fully Automated Analog IC Layout System from Netlist to GDSII

Hao Chen*, Mingjie Liu *, Biying Xu*, Keren Zhu *, Xiyuan Tang, Shaolan Li, Yibo Lin, Nan Sun and David Z. Pan

IEEE Design & Test, 2020.

Invited
*indicates equal contributions

C9. Exploring Logic Optimizations with Reinforcement Learning and Graph Convolutional Network

Keren Zhu, Mingjie Liu, Hao Chen, Zheng Zhao and David Z. Pan

2nd ACM/IEEE Workshop on Machine Learning for CAD (MLCAD),Virtual Event, Iceland, November 16-20, 2020.

preprint | source codes | slides

C8. Toward Silicon-Proven Detailed Routing for Analog and Mixed-Signal Circuits

Hao Chen, Keren Zhu, Mingjie Liu, Xiyuan Tang, Nan Sun and David Z. Pan

IEEE/ACM International Conference on Computer-Aided Design (ICCAD), November 02-05, 2020.

preprint | slides

C7. Effective Analog/Mixed-Signal Circuit Placement Considering System Signal Flow

Keren Zhu, Hao Chen, Mingjie Liu, Xiyuan Tang, Nan Sun and David Z. Pan

IEEE/ACM International Conference on Computer-Aided Design (ICCAD), November 02-05, 2020.

preprint | source codes | slides
Best Paper Candidate Nominated from Track

C6. An Efficient Training Framework for Reversible Neural Architectures

Zixuan Jiang, Keren Zhu, Mingjie Liu, Jiaqi Gu and David Z. Pan

European Conference on Computer Vision (ECCV), Glasgow, United Kingdom, August 23-27, 2020.

preprint | slides

C5. Closing the Design Loop: Bayesian Optimization Assisted Hierarchical Analog Layout Synthesis

Mingjie Liu, Keren Zhu, Xiyuan Tang, Biying Xu, Wei Shi, Nan Sun and David Z. Pan

ACM/IEEE Design Automation Conference (DAC), San Francisco, CA, July 19-23, 2020.

C4. Towards Decrypting the Art of Analog Layout: Placement Quality Prediction via Transfer Learning

Mingjie Liu *, Keren Zhu *, Jiaqi Gu, Linxiao Shen, Xiyuan Tang, Nan Sun and David Z. Pan

IEEE Design, Automation & Test in Europe Conference & Exhibition (DATE), Grenoble, France, Mar. 09-13, 2020.

preprint | slides | source codes
*indicates equal contributions

C3. S3DET: Detecting System Symmetry Constraints for Analog Circuits with Graph Similarity

Mingjie Liu, Wuxi Li, Keren Zhu, Biying Xu, Yibo Lin, Linxiao Shen, Xiyuan Tang, Nan Sun and David Z. Pan

IEEE/ACM Asia and South Pacific Design Automation Conference (ASPDAC), Beijing, China, January 13-16, 2020.

| codes for reference
Best Paper Award Nomination

2019

C2. MAGICAL: Toward Fully Automated Analog IC Layout Leveraging Human and Machine Intelligence

Biying Xu, Keren Zhu, Mingjie Liu, Yibo Lin, Shaolan Li, Xiyuan Tang, Nan Sun, and David Z. Pan

IEEE/ACM International Conference on Computer-Aided Design (ICCAD), Westminster, CO, USA, November 4-7, 2019.

Invited
preprint | slides

C1. GeniusRoute: A New Routing Paradigm Using Generative Neural Network Guidance for Analog Circuits

Keren Zhu, Mingjie Liu, Yibo Lin, Biying Xu, Shaolan Li, Xiyuan Tang, Nan Sun and David Z. Pan

IEEE/ACM International Conference on Computer-Aided Design (ICCAD), Westminster, CO, USA, November 4-7, 2019.

preprint | slides
Best Paper Candidate Nominated from Track

Preprints

P1. Provably Good Prim-Dijkstra Revisited: New Theory and a Practical Algorithm for a Classical VLSI Routing Problem with LLMs

arXiv preprint arXiv:2607.17005, 2026.

Code and reproducibility materials