RC-Scaled Timing-Driven Routing: Bridging Targeted Timing Optimization and Massively Parallel Global Routing
IEEE International Symposium on Circuits and Systems (ISCAS), Shanghai, China, May 24-27, 2026.
- † 通讯作者
- 已录用
Chuyu Wang
博士生
CODA lab · 复旦大学
2024年秋季加入课题组
近期研究包括数据流感知的存内计算版图与时序驱动全局布线。
与Xuan Zeng（曾璇）教授联合指导
教育经历
- 本科，复旦大学
工作与实习经历
- 实习生, 字节跳动
论文
DAMIL-DCIM+: Automated Dataflow-Aware Layout Synthesis for Digital CIM with Self-Assembled Bitcell Units and MILP-Based Optimization
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2025.
- † 通讯作者
- * 同等贡献
DAMIL-DCIM: A Digital CIM Layout Synthesis Framework with Dataflow-Aware Floorplan and MILP-Based Detailed Placement
IEEE Design, Automation & Test in Europe Conference & Exhibition (DATE), Lyon, France, March 31 - April 2, 2025.
- * 通讯作者
AI-Enabled Layout Automation for Analog and RF IC: Current Status and Future Directions
IEEE International Symposium on Radio-Frequency Integration Technology (RFIT), Chengdu, China, Aug. 28–30, 2024.
- † 通讯作者