RC-Scaled Timing-Driven Routing: Bridging Targeted Timing Optimization and Massively Parallel Global Routing
IEEE International Symposium on Circuits and Systems (ISCAS), Shanghai, China, May 24-27, 2026.
- † Corresponding authors
- Accepted
Chuyu Wang
Ph.D. student
CODA lab · Fudan University
With the group since Fall 2024
Recent work includes dataflow-aware computing-in-memory layout and timing-driven global routing.
With Prof. Xuan Zeng
Education
- B.S., Fudan
Experience
- Intern, ByteDance
Publications
DAMIL-DCIM+: Automated Dataflow-Aware Layout Synthesis for Digital CIM with Self-Assembled Bitcell Units and MILP-Based Optimization
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2025.
- † Corresponding authors
- * Equal contributions
DAMIL-DCIM: A Digital CIM Layout Synthesis Framework with Dataflow-Aware Floorplan and MILP-Based Detailed Placement
IEEE Design, Automation & Test in Europe Conference & Exhibition (DATE), Lyon, France, March 31 - April 2, 2025.
- * corresponding authors
AI-Enabled Layout Automation for Analog and RF IC: Current Status and Future Directions
IEEE International Symposium on Radio-Frequency Integration Technology (RFIT), Chengdu, China, Aug. 28–30, 2024.
- † Corresponding authors